Huawei is laying the groundwork for a very different kind of chip roadmap, one that does not rely on the same manufacturing assumptions that have shaped the industry for years. The company is targeting a process equivalent to 1.4 nm for its Kirin line by 2031 through a new approach called LogicFolding, a goal that puts its long-term ambitions in the same conversation as TSMC’s 14A node.
That direction matters because Huawei is pursuing it under sustained pressure from US sanctions that have been in place since 2019. Restrictions on semiconductors, software, and US-made technologies have slowed the company’s flagship chipset development, yet Huawei now appears to be pushing a more independent path rather than waiting for access to normalize.
A shift in strategy, not just in process size
Huawei’s latest approach moves away from the idea that chip progress must come primarily from shrinking physical dimensions. Instead, the company is emphasizing what it describes as a shift from geometric scaling to time scaling as a guiding principle for semiconductor and electronic systems.
He Tingbo, president of Huawei’s Semiconductor Business Unit, outlined that direction at the IEEE ISCAS 2026 symposium in Shanghai. The framing suggests that Huawei is trying to improve performance through design principles that reduce signal delay and support denser transistor layouts in a different way from the industry’s usual roadmap.
LogicFolding sits at the center of that plan. Huawei presents it as a design breakthrough intended to compress signal delay while improving transistor density in a more stable manner, which also points to a broader attempt to reduce dependence on conventional EUV lithography tools from ASML.
Testing beyond the concept stage
Huawei says the idea is not limited to theory. According to He, the new time-scaling approach has been tested on more than 381 chips over the past six years, covering use cases from smartphones to AI.
That detail suggests the company is building the framework as a multi-purpose platform rather than a one-off solution for a single device category. It also indicates that LogicFolding has been developing as part of a longer semiconductor roadmap, not just as a reaction to supply constraints.
The company is already preparing an early commercial step. The first Kirin chip built on the LogicFolding architecture is scheduled to arrive in autumn 2026 and is expected to power Huawei’s latest flagship device.
Why the 1.4 nm target stands out
Huawei’s long-term objective is to reach transistor density equivalent to TSMC’s 14A, or 1.4 nm, by 2031. That target signals more than a recovery effort, since it places Huawei’s ambitions at the edge of advanced chip development.
In semiconductor manufacturing, lower nm figures usually indicate smaller transistor dimensions and tighter spacing between components. That generally supports better efficiency, stronger performance, and lower power consumption, which is why the 1.4 nm target is so closely watched.
Huawei Central reported that LogicFolding-based chipsets are claimed to deliver a significant performance leap. Even without conventional access to the same technology stack used by leading global rivals, Huawei appears intent on staying in the race through a different engineering model.
Building a more self-reliant ecosystem
The manufacturing challenge remains central to the story. Huawei is reported to be working with SiCarrier, a Chinese company focused on developing domestic EUV equipment, as part of a wider effort to strengthen local semiconductor capabilities.
That collaboration matters because the obstacle is not only chip design. Manufacturing capacity and access to equipment are also critical, and the large funding being directed into this area reflects a broader push for a more self-sufficient ecosystem.
Seen in that light, the Kirin roadmap is not just about one product line. It is tied to a wider effort to strengthen China’s semiconductor independence at a time when global technology competition remains tightly constrained.
Source: www.suara.com
